Design Device for Subthreshold Slope in DG Fully Depleted SOI MOSFE

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Title	Design Device for Subthreshold Slope in DG Fully Depleted SOI MOSFE
Authors	Neha, Goel Manoj, Kumar Pandey
ORCID
Keywords	Fully depleted silicon on insulator (FDSOI) Threshold voltage Sub threshold slope
Type	Article
Date of Issue	2017
URI	http://essuir.sumdu.edu.ua/handle/123456789/65780
Publisher	Sumy State University
License	Copyright not evaluated
Citation	Neha, Goel Design Device for Subthreshold Slope in DG Fully Depleted SOI MOSFE [Текст] / Neha Goel, Manoj Kumar Pandey // Журнал нано- та електронної фізики. - 2017. - Т.9, № 1. - 01022. - DOI: 10.21272/jnep.9(1).01022.
Abstract	In this paper, we discuss how a short channel effects can be suppressed and how a threshold voltage fluctuation can be minimized and better control of subthreshold slope by the impact of the back gate bias and control of gate work function of a fully depleted SOI (Silicon-On-Insulator) MOSFET. The fluctuation in the threshold voltage and subthreshold slope are due to short channel effects. The Back gate voltage plays a significant role on the threshold voltage and thin buried oxide is used to suppress the short-channel effects and is used to keep a low value of the subthreshold slope are described in this paper. It is shown that how short channel effects can be suppressed in order to improve subthreshold slope.
Appears in Collections:	Журнал нано- та електронної фізики (Journal of nano- and electronic physics)