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Title | Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor |
Authors |
Vijh, M.
Gupta, R.S. Pandey, S. |
ORCID | |
Keywords |
Surrounding gate Tunnel FET Heterojunction Surface Potential Threshold Voltage Broken-gap |
Type | Article |
Date of Issue | 2017 |
URI | http://essuir.sumdu.edu.ua/handle/123456789/65797 |
Publisher | Sumy State University |
License | Copyright not evaluated |
Citation | Vijh, M. Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor [Текст] / M. Vijh, R.S. Gupta, S. Pandey // Журнал нано- та електронної фізики. - 2017. - Т.9, № 1. - 01030. - DOI: 10.21272/jnep.9(1).01030. |
Abstract |
Tunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has
captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor. This device,
due to its varied advantages, is considered in applications where devices are scaled down to deep submicron
level. Like MOSFETs, many geometries of TFETs have been studied and analyzed in the past few
years. This work, presents a two dimensional analytical model for a III-V Heterojunction Surrounding
Gate Tunneling Field Effect Transistor. 2-D Poisson’s equation in cylindrical coordinates has been solved
to derive the expression of Surface Potential and threshold voltage of the device. A broken gap GaSb/InAs
heterostructure has been considered in this work. Variation of potential profiles are shown with different
gate and drain biases, by varying radius of the transistor,and different gate metals. Also, variation of
threshold voltage is shown with respect to channel length and radius of the nanowire. |
Appears in Collections: |
Журнал нано- та електронної фізики (Journal of nano- and electronic physics) |
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