Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

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Title	Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit
Authors	Nehru, K. Nagarjuna, T. Vijay, G.
ORCID
Keywords	CNTFET ALU CMOS MOSFET Verilog CPL
Type	Article
Date of Issue	2017
URI	http://essuir.sumdu.edu.ua/handle/123456789/65958
Publisher	Sumy State University
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Citation	Nehru, K. Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit [Текст] / K. Nehru, T. Nagarjuna, G. Vijay // Журнал нано- та електронної фізики. – 2017. – Т.9, № 4. – 04018. – DOI: 10.21272/jnep.9(4).04018.
Abstract	This paper proposes the novel low power and area efficient ALU (Arithmetic and Logic Unit) using adder and multiplexers. The adder and multiplexer are realized by using CNTFET (Carbon Nano Tube Field Effect Transistor) A verilog model of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in cadence spice software. The proposed ALU is simulated using Monte carlo simulation at 0.9 sub threshold voltage tested with 45 nm technology for the measurement of power and transistor counts. The power consumption of CNTFET based ALU is found to be 45.67 % better than the existing technologies.
Appears in Collections:	Журнал нано- та електронної фізики (Journal of nano- and electronic physics)