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Title | Numerical Simulation and Mathematical Modeling of 3D DG SOI MOSFET with the Influence of Biasing with Back Gate |
Authors |
Neha, Goel
Manoj, Kumar Pandey |
ORCID | |
Keywords |
Fully Depleted Silicon on insulator (FDSOI) 3D analytical model Short channel effects (SCE) Bulk CMOS Surface potential Threshold voltage Drain induced barrier lowering (DIBL) |
Type | Article |
Date of Issue | 2017 |
URI | http://essuir.sumdu.edu.ua/handle/123456789/65996 |
Publisher | Sumy State University |
License | Copyright not evaluated |
Citation | Neha, Goel Numerical Simulation and Mathematical Modeling of 3D DG SOI MOSFET with the Influence of Biasing with Back Gate [Текст] / Neha Goel, Manoj Kumar Pandey // Журнал нано- та електронної фізики. - 2017. - Т.9, № 5. - 05002. - DOI: 10.21272/jnep.9(5).05002. |
Abstract |
Design consideration of a fully depleted SOI (Silicon-On-Insulator) MOSFET device by three dimensional
mathematical modeling is presented in this paper. To the best of our knowledge, when our device is
fabricated in nanometer regime, the threshold voltage changes due to various effects. Back gate voltage
plays a significant role on the controlling of threshold voltage. Separation of variable is used to solve the
Poisson’s three dimensional equation, analytically with suitable boundary conditions for the threshold
voltage of double gate SOI MOSFET with the influence of biasing with back gate. In this work, changes in
threshold voltage has been calculated and demonstrated that how short channel effects and DIBL can be
suppressed with application of Back Gate bias voltage. |
Appears in Collections: |
Журнал нано- та електронної фізики (Journal of nano- and electronic physics) |
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File | Size | Format | Downloads |
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Proof_JNEP_05002.pdf | 259.91 kB | Adobe PDF | 7716765 |
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