Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor

Abstract

Conditional branches are a serious issue in the pipelined processor. The branch direction and branch target address are determined and calculated by the processor after several cycles of the instruction decode, which results in the pipeline stall. Pipeline stall leads to control hazards in the processor and results in performance degradation. To increase the rate of the instruction flow in modern processors, branch prediction is used. Branch prediction provides an ideal speedup in performance of the processor. The processor predicts the direction in the branch prediction and determines instructions in accordance with the predicted path. The processor tests any prediction for the branch when the branch condition is calculated. If the prediction is incorrect, the processor will automatically abort all instructions taken along the wrong path and return the state to the address of the determined branch. An inaccurate branch predictor results in increased program run-time and leads to higher power consumption. Once the position of a branch is known, the actual target address of the next instruction must also be determined along the expected path. If the branch is expected not to be taken, the destination address is simply the address of the current branch plus the size of the command word. Unless the branch is to be taken, then the target depends on the branch type. The branch target buffer (BTB) can reduce branch efficiency by predicting the branch path and storing information used by branch. There are no stalls if the branch entry is found in BTB, and the calculation is accurate, or the penalty shall be two cycles or more. This paper focuses on the design and development of branch predictor with BTB for the fetch unit, which further integrates to an in-order pipelined RISC-V processor. The performance of the RISC-V core in terms of clock cycle latency, instruction per cycle (IPC), was measured and analyzed.