Si- and Ge-FinFET Inverter Circuits Optimization Based on Driver to Load Transistor Fin Ratio

Abstract

This paper proposes a novel method to adaptively select the best driver to load transistor fin ratio of six transistor (6T) FinFET-SRAMs according to the best values of noise margins and inflection voltages with a comparison between using Si and Ge as a semiconductor channel in a FinFET-SRAM cell. A 6T memory cell is considered as a primary memory cell that is widely used to design Static Random Access Memory (SRAM) and it has many applications in modern electronics. The 6T-SRAM cell is considered the first applicable unit to be implemented in an on-chip system using nanoscale FinFETs because of critical scaling issues of a SRAM cell of planar MOSFETs. The methodology for optimizing the driver to load transistor fin ratio will strongly depend on improving the noise margin and inflection voltage of the butterfly characteristics of the SRAM cell. The first step in this study of the 6T-FinFET-SRAM cell is to obtain the output characteristics (ID-VD) of FinFET. This research used simulation to generate the FinFET output characteristics and then used its data in a designed model by MATLAB to create the butterfly characteristics of the SRAM cell. The butterfly characteristics of 6T-Si- and Ge-FinFET-SRAM cell were investigated with fin ratios Np/Nn of 0.5, 1, 2, 3, 4, and 5. Noise margin and inflection voltage were used as critical factors to obtain the optimal fin ratio Np/Nn. Results indicate that the optimization strongly depends on the fin ratio for both Si and Ge semiconductors. Because of the channel fin shape with more channel current controlled, the results are completely different from a planar 6T-MOSFET-SRAM cell. For the 6T-Si-FinFET-SRAM cell, the optimized fin ratio was 2/1 and for the 6T-Ge-FinFET-SRAM cell, the optimized fin ratio was 1/4.