Please use this identifier to cite or link to this item: https://essuir.sumdu.edu.ua/handle/123456789/80515
Or use following links to share this resource in social networks: Recommend this item
Title Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor
Authors Arul Rathi, C.
Rajakumar, G.
Ananth Kumar, T.
Arun Samuel, T.S.
Keywords branch target buffer
pipeline
hazard
branch predictor
fetch
conditional and unconditional instruction
Type Article
Date of Issue 2020
URI https://essuir.sumdu.edu.ua/handle/123456789/80515
Publisher Sumy State University
License In Copyright
Citation Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor [Текст] / C. Arul Rathi, G. Rajakumar, T. Ananth Kumar, T.S. Arun Samuel // Журнал нано- та електронної фізики. – 2020. – Т. 12, № 5. – 05021. – DOI: 10.21272/jnep.12(5).05021.
Abstract Conditional branches are a serious issue in the pipelined processor. The branch direction and branch target address are determined and calculated by the processor after several cycles of the instruction decode, which results in the pipeline stall. Pipeline stall leads to control hazards in the processor and results in performance degradation. To increase the rate of the instruction flow in modern processors, branch prediction is used. Branch prediction provides an ideal speedup in performance of the processor. The processor predicts the direction in the branch prediction and determines instructions in accordance with the predicted path. The processor tests any prediction for the branch when the branch condition is calculated. If the prediction is incorrect, the processor will automatically abort all instructions taken along the wrong path and return the state to the address of the determined branch. An inaccurate branch predictor results in increased program run-time and leads to higher power consumption. Once the position of a branch is known, the actual target address of the next instruction must also be determined along the expected path. If the branch is expected not to be taken, the destination address is simply the address of the current branch plus the size of the command word. Unless the branch is to be taken, then the target depends on the branch type. The branch target buffer (BTB) can reduce branch efficiency by predicting the branch path and storing information used by branch. There are no stalls if the branch entry is found in BTB, and the calculation is accurate, or the penalty shall be two cycles or more. This paper focuses on the design and development of branch predictor with BTB for the fetch unit, which further integrates to an in-order pipelined RISC-V processor. The performance of the RISC-V core in terms of clock cycle latency, instruction per cycle (IPC), was measured and analyzed.
Appears in Collections: Журнал нано- та електронної фізики (Journal of nano- and electronic physics)

Views

China China
1
France France
910
Germany Germany
54224
Greece Greece
1
Hong Kong SAR China Hong Kong SAR China
1
India India
54226
Italy Italy
1
Lithuania Lithuania
1
Pakistan Pakistan
13275
Singapore Singapore
421605
South Korea South Korea
1
Taiwan Taiwan
1
Ukraine Ukraine
174
United Kingdom United Kingdom
1
United States United States
843211
Vietnam Vietnam
13288

Downloads

China China
1
France France
1
Germany Germany
54225
India India
843214
Iran Iran
1
Pakistan Pakistan
1
Singapore Singapore
1
South Korea South Korea
1
Ukraine Ukraine
173
United Arab Emirates United Arab Emirates
1
United Kingdom United Kingdom
1
United States United States
843212
Vietnam Vietnam
13289

Files

File Size Format Downloads
Arul_Rathi_jnep_5_2020.pdf 247 kB Adobe PDF 1754121

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.